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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ad1835a 2 adc, 8 dac, 96 khz, 24-bit - codecs features 5 v stereo audio system with 3.3 v tolerant digital interface supports up to 96 khz sample rates 192 khz sample rate available on 1 dac supports 16-/20-/24-bit word lengths multibit - modulators with perfect differential linearity restoration for reduced idle tones and noise floor data directed scrambling dacs?east sensitive to jitter differential output for optimum performance adcs: ?5 db thd + n, 105 db snr, and dynamic range dacs: ?5 db thd + n, 108 db snr, and dynamic range on-chip volume controls per channel with 1024-step linear scale dac and adc software controllable clickless mutes digital de-emphasis processing functional block diagram outlp1 outln1 outrp1 outrn1 control port clock filtd filtr adclp adcln adcrp adcrn dlrclk dbclk dsdata1 dsdata2 dsdata3 dsdata4 mclk asdata abclk alrclk odvdd dvdd av d d av d d dvdd a gnd a gnd a gnd a gnd dgnd dgnd cin clatch cclk cout digital filter pd / rst m /s - adc serial data i/o port v ref volu me digital filter volu me - dac digital filter - adc ad1835a volu me digital filter volu me - dac volu me digital filter volu me - dac volu me digital filter volu me - dac outlp2 outln2 outrp2 outrn2 outlp3 outln3 outrp3 outrn3 outlp4 outln4 outrp4 outrn4 product overview the ad1835a is a high performance, single-chip codec fea- turing four stereo dacs and one stereo adc. each dac comprises a high performance digital interpolation filter, a multibit - modulator featuring analog devices?patented technology, and a continuous-time voltage out analog section. (continued on page 11) supports 256 f s , 512 f s , and 768 f s master mode clocks power-down mode plus soft power-down mode flexible serial data port with right-justified, left- justified, i 2 s compatible, and dsp serial port modes tdm interface mode supports 8-in/8-out using a single sharc sport 52-lead mqfp plastic package applications dvd video and audio players home theater systems automotive audio systems audio/visual receivers digital audio effects processors
rev. a e2e ad1835aespecifications test conditions supply voltages (avdd, dvdd) 5.0 v ambient temperature 25
rev. a ad1835a e3e parameter min typ max unit adc decimation filter, 96 khz * pass band 43.54 khz pass-band ripple 0.01 db stop band 52.46 khz stop-band attenuation 120 db group delay 460 s dac interpolation filter, 48 khz * pass band 21.77 khz pass-band ripple 0.06 db stop band 28 khz stop-band attenuation 55 db group delay 340 s dac interpolation filter, 96 khz * pass band 43.54 khz pass-band ripple
rev. a e4e ad1835a timing specifications parameter min max unit comments master clock and reset t mh mclk high 15 ns t ml mclk low 15 ns t pdr pd rst sp prt p p ds dts tr d dt r s ts tr t r t t d td ts tts tr dsrprt ms d d d d d d s ds drs tdr d dr dr dds dsdts tdr dd dsdt dr pms d d d d d d s ds drs tdr d dr dr dds dsdts tdr dd dsdtd dr dsrprt mm d d mr d rd dd sdtd ms s s rs tr r r dd sdtd pmm pd d mr pd rd pdd sdtd
rev. a ad1835a e5e parameter min max unit comments tdm256 mode (master, 48 khz and 96 khz) t tbd bclk delay 40 ns from mclk rising t fsd fstdm delay 5 ns from bclk rising t tabdd asdata delay 10 ns from bclk rising t tdds dsdata1 setup 15 ns to bclk falling t tddh dsdata1 hold 15 ns from bclk falling tdm256 mode (slave, 48 khz and 96 khz) f ab bclk frequency 256 f s t tbch bclk high 17 ns t tbcl bclk low 17 ns t tfs fstdm setup 10 ns to bclk falling t tfh fstdm hold 10 ns from bclk falling t tbdd asdata delay 15 ns from bclk rising t tdds dsdata1 setup 15 ns to bclk falling t tddh dsdata1 hold 15 ns from bclk falling tdm512 mode (master, 48 khz) t tbd bclk delay 40 ns from mclk rising t fsd fstdm delay 5 ns from bclk rising t tabdd asdata delay 10 ns from bclk rising t tdds dsdata1 setup 15 ns to bclk falling t tddh dsdata1 hold 15 ns from bclk falling tdm512 mode (slave, 48 khz ) f ab bclk frequency 512 f s t tbch bclk high 17 ns t tbcl bclk low 17 ns t tfs fstdm setup 10 ns to bclk falling t tfh fstdm hold 10 ns from bclk falling t tbdd asdata delay 15 ns from bclk rising t tdds dsdata1 setup 15 ns to bclk falling t tddh dsdata1 hold 15 ns from bclk falling auxiliary interface (48 khz and 96 khz) t axds aauxdata setup 10 ns to auxbclk rising t axdh aauxdata hold 10 ns from auxbclk rising f abp auxbclk frequency 64 f s slave mode t axbh auxbclk high 15 ns t axbl auxbclk low 15 ns t axls auxlrclk setup 10 ns to auxbclk rising t axlh auxlrclk hold 10 ns from auxbclk rising master mode t auxlrclk auxlrclk delay 15 ns from auxbclk falling t auxbclk auxbclk delay 20 ns from mclk rising specifications subject to change without notice. mclk t mh p d / rst t ml t pdr t mclk figure 1. mclk and pd rst t
rev. a e6e ad1835a caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1835a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. temperature range parameter min typ max unit specifications guaranteed 25
rev. a ad1835a e7e pin function descriptions input/ pin number mnemonic output description 1, 39 dvdd digital power supply. connect to digital 5 v supply. 2c latch i latch input for control data. 3 cin i serial control input. 4 pd rst pdr d t d tp dp tr dr trp drp dd ps td r m s dmss dr dr d d dd d dsdt ddr d r dr m m ddd ddps sdt dsd t d d prt d dd trp tr tp t trp tr tp t pd rst t ddd t tp tr trp t tp tr trp d dr d dd td tr d m s d dd d dp dr drp d d dd t sdt ddd m r dsdt dsdt dsdt dsdt ddd dd d tpw s
rev. a e8e ad1835aetypical performance characteristics frequency e normalized to f s 05 magnitude e db 10 e150 15 e100 e50 0 tpc 1. adc composite filter response frequency e hz e30 020 5 magnitude e db 10 15 e25 e20 e15 e10 e5 0 5 tpc 2. adc high-pass filter response, f s = 48 khz frequency e normalized to f s e150 0 2.0 0.5 magnitude e db 1.0 1.5 0 e100 e50 tpc 3. adc composite filter response (pass-band section) frequency e hz e30 020 5 magnitude e db 10 15 e25 e20 e15 e10 e5 0 5 tpc 4. adc high-pass filter response, f s = 96 khz frequency e khz 0 e50 e150 magnitude e db e100 0 200 50 100 150 tpc 5. dac composite filter response, f s = 48 khz 0 e50 e150 e100 0 200 50 100 150 frequency e khz magnitude e db tpc 6. dac composite filter response, f s = 96 khz
rev. a ad1835a e9e 0 e50 0 200 50 100 150 e100 e150 frequency e khz magnitude e db tpc 7. dac composite filter response, f s = 192 khz 0.10 0.05 e0.10 020 51015 0 e0.05 frequency e khz magnitude e db tpc 8. dac composite filter response, f s = 48 khz (pass-band section) 0.2 0.1 e0.2 050 10 20 30 40 0 e0.1 frequency e khz magnitude e db tpc 9. dac composite filter response, f s = 96 khz (pass-band section) 0.10 0.05 e0.10 0 100 20 40 60 80 0 e0.05 frequency e khz magnitude e db tpc 10. dac composite filter response, f s = 192 khz (pass-band section)
rev. a e10e ad1835a definitions dynamic range the ratio of a full-scale input signal to the integrated input noise in the pass band (20 hz to 20 khz), expressed in decibels (db). dynamic range is measured with a e60 db input signal and is equal to (s/[thd + n]) + 60 db. note that spurious harmonics are below the noise with a e60 db input, so the noise level es tablishes the dynamic range. the dynamic range is specified with and without an a-weight filter applied. signal-to-(total harmonic distortion + noise)[s/(thd + n)] the ratio of the root-mean-square (rms) value of the fundamen- tal input signal to the rms sum of all other spectral components in the pass band, expressed in decibels (db). pass band the region of the frequency spectrum unaffected by the attenu- ation of the digital decimator?s filter. pass-band ripple the peak-to-peak variation in amplitude response from equal- amplitude input signal frequencies within the pass band, expressed in decibels. stop band the region of the frequency spectrum attenuated by the digital decimator?s filter to the degree specified by stop-band attenua tion. gain error with a near full-scale input, the ratio of actual output to ex pected output, expressed as a percentage. interchannel gain mismatch with identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels. gain drift change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per
rev. a ad1835a e11e (continued from page 1) each dac has independent volume control and clickless mute functions. the adc comprises two 24-bit conversion channels with multibit - modulators and decimation filters. the ad1835a also contains an on-chip reference with a nominal value of 2.25 v. the ad1835a contains a flexible serial interface that allows glueless connection to a variety of dsp chips, aes/ebu receivers, and sample rate converters. the ad1835a can be configured in left-justified, right-justified, i 2 s, or dsp com- patible serial modes. control of the ad1835a is achieved by an spi compatible serial port. while the ad1835a can be oper- ated from a single 5 v supply, it also features a separate supply pin for its digital interface which allows the device to be inter- faced to other devices using 3.3 v power supplies. the ad1835a is available in a 52-lead mqfp package and is specified for the industrial temperature range of e40 m s ddddd w dw d tdd d drd tdm dd dtdd dt d r ttd t dd dd tdd t tt t s s r s dsm dm mtd t mt mt dt mmm tmd dd md m mm d m sdsr tdd m t mm tdsrs sr r dr sdsr tdd mm tm d t
rev. a e12e ad1835a dac engine cl ock scaling 1 2 2/3 mclk dac i/p in terpolation fi lter ? ? pd rst pd rst d t rd sp psr tds t p ttr
rev. a ad1835a e13e the format is similar to the motorola spi format except the input data-word is 16 bits wide. the maximum serial bit clock frequency is 12.5 mhz and may be completely asynchronous to the sample rate of the adcs and dacs. figure 3 shows the format of the spi signal. serial data ports?data format the adc serial data output mode defaults to the popular i 2 s format, where the data is delayed by 1 bclk interval from the edge of the lrclk. by changing bits 6 to 8 in adc control register 2, the serial mode can be changed to right-justified (rj), left-justified dsp (dsp), or left-justified (lj). in the rj mode, it is necessary to set bits 4 and 5 to define the width of the data-word. the dac serial data input mode defaults to i 2 s. by changing bits 5, 6, and 7 in dac control register 1, the mode can be changed to rj, dsp, lj, packed mode 1, or packed mode 2. the word width defaults to 24 bits but can be changed by re programming bits 3 and 4 in dac control register 1. packed modes the ad1835a has a packed mode that allows a dsp or other controller to write to all dacs and read all adcs using one input data pin and one output data pin. packed mode 256 refers to the number of bclks in each frame. the lrclk is low while data from a left channel dac or adc is on the data pin and high while data from a right channel dac or adc is on the data pin. dac data is applied on the dsdata1 pin and adc data is available on the asdata pin. figures 7 to 12 show the timing for the packed mode. packed mode is available for 48 khz and 96 khz. auxiliary (tdm) mode a special auxiliary mode is provided to allow three external stereo adcs to be interfaced to the ad1835a to provide 8-in/8-out operation. in addition, this mode supports glueless interface to a single sharc dsp serial port, allowing a sharc dsp to access all eight channels of analog i/o. in this special mode, many pins are redefined; see table iv for a list of rede fined pins. the auxiliary and tdm interfaces are independently configurable to operate as masters or slaves. when the auxiliary interface is set as a master, by programmi ng the au xiliary m ode bit in adc control register 2, the auxlrclk and auxbclk ar e generated by the ad1835a. when the auxiliary interface is set as a slave, the auxlrclk and auxbclk need to be generated by an external adc as shown in figure 15. the tdm interface can be set to operate as a master or slave by connecting the m sddddd stdm dstdm sr mmm r sdt r sdt r sdt r sdt t rt t rt t rt ms ms ms ms ms ms ms ms s s s s s s s s tstdmdtsttspr s mdtsttspr rtstdmdstmrtspr dspmdtsttspr s ts dspmddstdt rrmprtst s ptrdspmdws s rsrm rtmprtdrstmd ssm
rev. a e14e ad1835a t als abclk alrclk asdata lef t-justified mode asdata right-ju stified mode lsb asdata i 2 s compatible mode t abh t abl msb msb e 1 msb msb t abdd t alh figure 5. adc serial mode timing t dls dbclk dlrclk dsdata left-j ustified mode dsdata right-ju stified mode lsb dsdata i 2 s compatible mode t dbh t dbl t dds msb msb e 1 t ddh t dds msb t ddh t dds t dds t ddh t ddh msb t dlh figure 6. dac serial mode timing
rev. a ad1835a e15e lrclk bclk adc data slot 1 left slot 2 slot 5 right slot 6 msb msb e 1 msb e 2 16 bclks 128 bclks slot 3 slot 4 slot 7 slot 8 figure 7. adc packed mode 128 lrclk bclk adc data slot 1 left slot 2 slot 5 right slot 6 msb msb e 1 msb e 2 32 bclks 256 bclks slot 3 slot 4 slot 7 slot 8 figure 8. adc packed mode 256 lrclk bclk dac data slot 1 left 1 slot 5 right 1 msb msb e 1 msb e 2 16 bclks 128 bclks slot 2 left 2 slot 3 left 3 slot 4 left 4 slot 6 right 2 slot 7 right 3 slot 8 right 4 figure 9. dac packed mode 128 lrclk bclk dac data slot 1 left 1 slot 5 right 1 msb msb e 1 msb e 2 32 bclks 256 bclks slot 2 left 2 slot 3 left 3 slot 4 left 4 slot 6 right 2 slot 7 right 3 slot 8 right 4 figure 10. dac packed mode 256 t als abclk alrclk asdata t abh t abl msb msb e 1 t alh t abdd figure 11. adc packed mode timing t dls dbclk dlrclk dsdata t dbh t dbl t dds msb msb e 1 t ddh t dlh figure 12. dac packed mode timing
rev. a e16e ad1835a table iv. pin function changes in auxiliary mode pin name i 2 s mode auxiliary mode as data (o) i 2 s data out, internal adc tdm data out to sharc. dsdata1 (i) i 2 s data in, internal dac1 tdm data in from sharc. dsdata2 (i)/aauxdata1 (i) i 2 s data in, internal dac2 aux-i 2 s data in 1 (from ex ternal adc). dsdata3 (i)/aauxdata2 (i) i 2 s data in, internal dac3 aux-i 2 s data in 2 (from ex ternal adc). dsdata4 (i)/aauxdata3 (i) i 2 s data in, internal dac4 aux-i 2 s data in 3 (from ex ternal adc). alrclk (o) lrclk for adc tdm frame sync out to sharc (fstdm). abclk (o) bclk for adc tdm bclk out to sharc. dlrclk (i)/auxlrclk(i/o) lrclk in/out internal dacs aux lrclk in/out. driven by ext ernal lrclk from adc in slave mode. in master mode, driven by mclk/512. dbclk (i)/auxbclk(i/o) bclk in/out internal dacs aux bclk in/out. driven by ex t ernal bclk from adc in slave mode. in master mode, driven by mclk/8. fstdm inte rnal adc l1 aux_adc l2 aux_adc l3 aux_adc l4 inte rnal adc r1 aux_adc r2 aux_adc r3 aux_adc r4 inte rnal dac l1 inte rnal dac l2 inte rnal dac l3 inte rnal dac r1 inte rnal dac r2 inte rnal dac r3 left right i 2 s e msb right i 2 s e msb left bclk tdm asdata1 tdm (out) asdata dsdata1 tdm (in) dsdata1 aux lrclk i 2 s (from aux adc no. 1) aux bclk i 2 s (from aux adc no. 1) aauxdata1 (in) (from aux adc no. 1) aauxdata2 (in) (from aux adc no. 2) aauxdata3 (in) (from aux adc no. 3) aux bclk frequency is 64 frame rate; tdm bclk frequency is 256 frame rate. tdm interface aux e i 2 s in terface 32 32 msb tdm msb tdm i 2 s e msb right i 2 s e msb left i 2 s e msb right i 2 s e msb left inte rnal dac l4 inte rnal dac r4 msb tdm msb tdm 1st ch 1st ch 8th ch 8th ch figure 13. auxiliary mode timing
rev. a ad1835a e17e 30mhz 12.288mhz sharc is always running in slave mode (interrupt-driven). fsync-tdm (rfs) rxclk rxdata tfs (nc) txclk txdata asdata fstdm bclk dsdata1 lrclk bclk data mclk adc no. 2 slave sharc ad1835a master mclk dsdata3/aauxdata2 dsdata2/aauxdata1 dlrclk/auxlrclk lrclk bclk data mclk adc no. 3 slave lrclk bclk data mclk adc no. 1 slave dsdata4/aauxdata3 dbclk/auxbclk figure 14. auxiliary mode connection (master mode) to sharc 30mhz 12.288mhz sharc is always running in slave mode (interrupt-driven). fsync-tdm (rfs) rxclk rxdata tfs (nc) txclk txdata asdata fstdm bclk dsdata1 lrclk bclk data mclk adc no. 2 slave sharc ad1835a slave mclk dsdata3/aauxdata2 dsdata2/aauxdata1 dlrclk/auxlrclk lrclk bclk data mclk adc no. 3 slave lrclk bclk data mclk adc no. 1 master dsdata4/aauxdata3 dbclk/auxbclk figure 15. auxiliary mode connection (slave mode) to sharc
rev. a e18e ad1835a control/status registers the ad1835a has 15 control registers, 13 of which are used to set the operating mode of the part. the other two registers, adc peak 0 and adc peak 1, are read-only and should not be pro grammed. each of the registers is 10 bits wide with the exception of the adc peak reading registers, which are six bits wide. writing to a control register requires a 16-bit data frame to be transmitted. bits 15 to 12 are the address bits of the re quired register. bit 11 is a read/write bit. bit 10 is reserved and should always be programmed to 0. bits 9 to 0 contain the 10-bit value that is to be written to the register or, in the case of a read operation, the 10-bit register contents. figure 3 shows the format of the spi read and write opera tion. dac control registers the ad1835a register map has 10 registers that are used to con trol the functionality of the dac section of the part. the function of the bits in these registers is discussed in the following sections. sample rate these bits control the sample rate of the dacs. based on a 24.576 mhz imclk, sample rates of 48 khz, 96 khz, and 192 khz are available. the mclk scaling bits in adc control 3 should be programmed appropriately, based on the master clock frequency. power-down/reset this bit controls the power-down status of the dac section. by default, normal mode is selected, but by setting this bit, the digital section of the dac stage can be put into a low power mode, thus reducing the digital current. the analog output section of the dac stage is not powered down. dac data-word width these two bits set the word width of the dac data. compact disk (cd) compatibility may require 16 bits, but many modern digital audio formats require 24-bit sample resolution. dac data format the ad1835a serial data interface can be configured to be compatible with a choice of popular interface formats, including i 2 s, lj, rj, or dsp modes. details of these interface modes are given in the serial data port section. de-emphasis the ad1835a provides built-in de-emphasis filtering for the three standard sample rates of 32.0 khz, 44.1 khz, and 48 khz. mute dac each of the eight dacs in the ad1835a has its own indepen dent mute control. setting the appropriate bit will mute the dac output. the ad1835a uses a clickless mute function that at tenu- ates the output to approximately e100 db over a number of cycles. stereo replicate setting this bit copies the digital data sent to the stereo pair dac1 to the three other stereo dacs in the system. this allows all four stereo dacs to be driven by one digital data stream. note that in this mode, dac data sent to the other dacs is ignored. dac volume control each dac in the ad1835a has its own independent volume control. the volume of each dac can be adjusted in 1024 linear steps by programming the appropriate register. the default value for this register is 1023, which provides no attenuation, i.e., full volume. adc control registers the ad1835a register map has five registers that are used to control the functionality and read the status of the adcs. the function of the bits in each of these registers is discussed in the following sections. adc peak level these two registers store the peak adc result from each chan- nel when the adc peak readback function is enabled. the peak result is stored as a 6-bit number from 0 db to e63 db in 1 db steps. the value contained in the register is reset once it has been read, allowing for continuous level adjustment as required. note that the adc peak level registers use the six most signifi- cant bits in the register to store the results. sample rate this bit controls the sample rate of the adcs. based on a 24.576 mhz imclk, sample rates of 48 khz and 96 khz are available. the mclk scaling bits in adc control 3 should be programmed appropriately based on the master clock frequency. adc power-down this bit controls the power-down status of the adc section and operates in a manner similar to the dac power-down. high-pass filter the adc signal path has a digital high-pass filter. enabling this filter will remove the effect of any dc offset in the analog input signal from the digital output codes. adc data-word width these two bits set the word width of the adc data. adc data format the ad1835a serial data interface can be configured to be compatible with a choice of popular interface formats, including i 2 s, lj, rj, or dsp modes. master/slave auxiliary mode when the ad1835a is operating in the auxiliary mode, the auxiliary adc control pins, auxbclk and auxlrclk, which connect to the external adcs, can be set to operate as a master or slave. if the pins are set in slave mode, one of the external adcs should provide the lrclk and bclk signals. adc peak readback setting this bit enables adcs peak reading. see the adcs section for more information.
rev. a ad1835a e19e table v. control register map register address register name description type width reset setting (hex) 0000 dacctrl1 dac control 1 r/ w dtr d r w d d r w d dr r w d d r w d dr r w d d r w d dr r w d d r w d dr r w dp dp r dp drp r dtr d r w dtr d r w dtr d r w r r r w r t d dd dd pd r w ww w
rev. a e20e ad1835a table x. adc control 1 function adc sample address r/ w w ww w w w
rev. a ad1835a e21e cascade mode dual ad1835a cascade the ad1835a can be cascaded to an additional ad1835a which, in addition to six external stereo adcs, can be used to create a 32-channel audio system with 16 inputs and 16 outputs. the cascade is designed to connect to a sharc dsp and oper- ates in a time division multiplexing (tdm) format. figure 16 shows the connection diagram for cascade operation. the digital interface for both parts must be set to operate in auxiliary 512 mode by programming adc control register 2. ad1835a no. 1 is set as a master device by connecting the m sdd d m sddd m pd rst wd tsr d t d tdsr dw srd d sr dd d s r sdt dsdt r sdt dsdt d mstr d s sr s dt r d s dt r d s dt r d s dt r d s dt r d s dt r r dt dt dt r dt dt dt dr rs r t dt ts dd dd r r r r dd r r r r ts rs dt dd r r r r dd r r r r dr ms ms s dt ms ms s dr dtr ddt
rev. a e22e ad1835a 5.76k 100pf npo a udio input 600z + 47 f 5.76k 120pf npo v ref 5.76k 5.76k v ref 750k 237 1nf npo 237 1nf npo 100pf npo adcxp adcxn op275 op275 figure 18. typical adc input filter circuit 3.01k 11k 270pf npo 560pf npo 68pf npo 11k 150pf npo 1.5k 5.62k 5.62k 604 2.2nf npo v bias (2.25v) outx a udio output op275 figure 19. typical dac output filter circuit
rev. a ad1835a e23e outline dimensions 52-lead metric quad flat package [mqfp] (s-52-1) dimensions shown in millimeters seating plane view a 2.45 max 1.03 0.88 0.73 top view (pins down) 1 39 40 13 14 27 26 52 pin 1 0.65 bsc 13.45 13.20 sq 12.95 7.80 ref 10.20 10.00 sq 9.80 0.40 0.22 7 0 2.20 2.00 1.80 0.13 min coplanarity 0.25 max 10 6 2 0.23 0.11 compliant to jedec standards ms-022-ac.
rev. a c03624e0e12/03(a) e24e ad1835a revision history location page 12/03?data sheet changed from rev. 0 to rev. a. changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 deleted clock signals section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 added ad1835a clocking scheme section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 added table ii and table iii and renumbered following tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 updated figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 updated auxiliary (tdm mode) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 updated figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 updated figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 added new figures 7 and 8 and renumbered subsequent figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 updated figures 11 and 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 edits to table xi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 updated table viii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 updated figure 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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